Marvell introduced the industry’s first 64 Gbps per wire bi-directional die-to-die (D2D) interconnect IP in 2nm, targeting next-generation XPUs for AI and cloud infrastructure. The technology, also available in 3nm, enables simultaneous two-way connectivity at 32 Gbps per direction on a single wire. With bandwidth density exceeding 30 Tbps/mm, the design delivers more than triple the density of equivalent UCIe implementations while using just 15% of the silicon area of conventional approaches.
The new D2D IP incorporates adaptive power management that dynamically responds to bursty data center traffic, reducing interface power consumption by up to 75% under normal conditions and 42% during peak usage. Reliability features include redundant lanes and automatic lane repair to improve yield and lower bit error rates. Marvell is delivering the interconnect as part of a complete stack—spanning PHY, application bridge, link layers, and physical interconnect—allowing chipmakers to accelerate time-to-market for custom XPUs.
The announcement builds on Marvell’s recent 2nm milestones, including its demonstration of working silicon in March 2025 and the introduction of 2nm SRAM earlier this year. The new D2D interconnect underscores Marvell’s broader custom silicon strategy, which spans advanced SerDes, silicon photonics, co-packaged optics, custom HBM, SoC fabrics, PCIe Gen 7 interfaces, and optical I/O.
- 64 Gbps per wire bi-directional interface IP in 2nm and 3nm
- 32 Gbps simultaneous two-way connectivity on a single wire
- Bandwidth density >30 Tbps/mm, 3x that of UCIe at equivalent speeds
- Adaptive power management cuts interface power up to 75%
- Redundant lanes and automatic repair improve resiliency and yield
- Delivered as a turnkey solution with PHY, bridge, link layers, and interconnect
“The 64 Gbps bi-directional D2D interface IP marks an industry first and reflects our commitment to pioneering technologies that enhance performance while reducing total cost of ownership for next-generation AI devices,” said Will Chu, senior vice president of Custom Cloud Solutions at Marvell.
🌐 Analysis: Marvell’s push into 2nm with D2D technology highlights the growing importance of intra-package interconnects as chipmakers shift toward disaggregated architectures. Competing standards such as UCIe aim to unify the ecosystem, but Marvell is carving out a differentiated position with higher bandwidth density and advanced power management. The move aligns with recent advances from rivals like Broadcom, which has emphasized PCIe Gen 7 and co-packaged optics, and underscores the race to optimize die-to-die links for AI accelerators and custom silicon platforms.
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