Marvell has begun sampling the industry’s first 1.6T Ethernet PHY with 100G PAM4 electrical input/outputs (I/Os) in 5nm, enabling next-generation 100G serial-based 400G and 800G Ethernet links for high-density switches. The doubling of the signaling rate creates signal integrity challenges, driving the need for retimer devices for high port count switch designs. It’s critical that retimer and gearboxes used for these applications are extremely power efficient. Implemented in the latest 5nm node, the Marvell 800GbE PHY provides a 40% savings in I/O power compared to existing 50G PAM4 based I/Os.
The Marvell 1.6T PHY incorporates the company’s 112G 5nm SerDes solution that was announced in November of last year, offering breakthrough performance with the ability to operate at 112G PAM4 across channels with >40dB insertion loss. This 112G 5nm SerDes technology will be designed in Marvell’s industry-proven Prestera® switch portfolio across data center, enterprise and carrier segments. It has also been adopted for use by multiple customers of Marvell’s 5nm ASIC offering in high-performance infrastructure applications across a variety of markets.
The company says its new Alaska C PHY accelerates the transition to 100G serial interconnects and doubles the bandwidth speeds of the previous generation of PHYs to bring scalability for performance-critical cloud workloads and applications such as artificial intelligence and machine learning.
Marvell notes that its new 88X93160 is the industry’s first PHY device fully compliant with IEEE’s 802.3ck standards for 100G serial I/Os and the Ethernet Technology Consortium’s 800GbE specifications. The device supports Gearboxing functionality which helps data center operators get the full bandwidth capabilities of the switch ASICs with 100G serial I/Os while interfacing with existing 50G PAM4 based 400G optical modules.
“Data center demand for 400GbE and beyond is experiencing exponential growth,” said Achyut Shah, senior vice president and general manager of Marvell’s PHY business unit. “We are very proud to offer the industry’s first dual 1.6T PHY with 100G PAM4 I/Os designed for cloud data centers. Our 112G SerDes in 5nm boasts industry-leading power and greatly enhances the value that high-speed Ethernet brings to cloud data center applications.”
Marvell completes acquisition of Inphi
Marvell Technology completed its previously announced acquisition of Inphi Corporation. The combination creates a U.S. semiconductor powerhouse positioned for end-to-end technology leadership in data infrastructure.“I am excited to welcome the Inphi team to Marvell and look forward to realizing the tremendous value creation potential of this combination for our customers, employees and shareholders. Together we will have the portfolio, capabilities,…
Marvell announces first 112G 5nm SerDes
Marvell introduced the first 112G 5nm SerDes solution that has been validated in hardware. The company also confirmed that it has recently secured a new custom ASIC design win customer that will embed this new IP to build next generation top-of-rack (ToR) and spine switches for leading hyperscale data centers.The Marvell 5nm SerDes solution doubles the bandwidth of current systems based on 56G while enabling the deployment of 112G I/Os. The device…
