Marvell has introduced a production-ready, modular multi-die packaging platform that enables next-generation custom AI accelerators to scale beyond the limits of traditional monolithic silicon designs. The platform integrates a novel redistribution layer (RDL) interposer that serves as an alternative to silicon interposers, offering lower power consumption, shorter die-to-die interconnects, and improved chiplet yields. The system is already qualified with a major hyperscaler and is ramping into production for data center infrastructure deployments.
The new packaging approach supports multi-die implementations up to 2.8 times larger than conventional single-chip solutions and integrates up to four HBM3/3E memory stacks across 1,390 mm² of silicon using six RDL layers. Unlike conventional interposers that span entire chiplet packages, Marvell said its modular RDL design connects only the necessary regions, reducing material costs and enabling defective dies to be swapped without discarding the full assembly. The platform also allows integration of passive devices to reduce signal noise and supports future migration to HBM4.
The advanced packaging innovation builds on Marvell’s broader custom XPU portfolio, which includes co-packaged optics (CPO) and advanced HBM integration, addressing the growing need for scalable, energy-efficient AI compute. The company is positioning its platform as a critical enabler for hyperscaler-designed AI chips that require aggressive power, performance, and footprint optimization.
- Enables 2.8x larger AI accelerator silicon than single-die implementations
- Uses modular RDL interposers instead of full silicon interposers
- Integrates up to four HBM3/3E memory stacks with six-layer RDL
- Reduces power, interconnect length, and cost while improving chiplet yield
- Production-qualified with hyperscalers; supports roadmap to HBM4
“Advanced packaging is one of the primary vehicles for advancing compute density in AI clusters and cloud,” said Will Chu, SVP and GM of Custom Cloud Solutions at Marvell. “Without it, AI infrastructure would be significantly more expensive and power-hungry.”
“The most complicated issue in the AI/ML solution design is to create an effective power delivery network, as GPUs are increasingly using more power. SEMCO is proud to have collaborated with Marvell to create a leading power delivery solution using its custom designed silicon capacitors and passive components,” said Taegon Lee, executive vice president and head of the Strategic Marketing Center at Samsung Electro-Mechanics (SEMCO). “The ecosystem approach we collectively took in developing this solution will rapidly become the norm. We look forward to continued collaboration with Marvell.”
- What are Interposers? Interposers are foundational layers used in advanced semiconductor packaging to connect multiple dies—such as CPUs, GPUs, and memory—within a single package. Traditionally made of silicon, interposers provide high-density wiring and serve as a bridge for electrical signals between stacked or side-by-side components, ensuring tight signal integrity, power delivery, and thermal performance. They enable heterogeneous integration, allowing chiplets with different functions and process nodes to communicate efficiently. However, silicon interposers are costly and complex to manufacture, leading to alternative approaches like redistribution layer (RDL) interposers, which offer lower material costs, greater design flexibility, and improved scalability for multi-die architectures, particularly in AI and high-performance computing applications.
