Microsemi introduced a new family of network synchronization phase-locked loops (PLLs) for Synchronous Ethernet (SyncE), IEEE 1588 and optical transport network (OTN).
The company said its new miTimePLL new products have one third the jitter and half the footprint of current devices, which, in combination with the company’s new miTimePLL technology, is specifically designed to address the demands of phase alignment performance required by networks such as wireless infrastructure.
Microsemi’s ZL307xx and ZL306xx family of network synchronization PLLs offers 180 femtoseconds (fs) typical jitter, ensuring a single chip, small footprint, low cost synchronization solution for 10GbE to 100GbE applications. These devices come with new features vital for network applications requiring phase alignment, including any-to-any frequency, better than 2 ns input/output (I/O) alignment, embedded 1 pulse per second (ePPS), time of day (ToD) registers, reference/synchronization inputs, and full monitoring and hitless reference switching between GPS/SyncE/1588. Microsemi’s ePPS is already providing a simple solution for chassis systems with limited backplane pins by combining phase into a high speed clock, thereby using a single pin, where before two were required.
“Microsemi has a long history in IEEE 1588 PLL devices dating back to 2008 with our first product introduction, and our 1588 solutions are widely used within tier 1 telecommunications equipment vendors. We continue to invest strongly to drive our technologies forward, meeting new challenges to stay ahead of the competition with ultra-low jitter on our new miTimePLL devices—providing a highly integrated, cost-effective solution for our customers,” said Maamoun Seido, vice president and business unit manager of Microsemi’s timing products. “Customers can remain confident in our capabilities, as these products enable them to handle phase alignment seamlessly within their equipment with a smaller footprint and attractive price point.”
