Napatech launched its new F3070X Data Processing Unit (DPU) today, a 400G acceleration platform built on Altera’s Agilex FPGA and Intel Xeon D processor technology. The DPU targets AI, cloud, telecom, and enterprise datacenters with a design focused on ultra-low latency, flexibility, and hardware-level security. The platform is part of Napatech’s expanding portfolio of SmartNICs and DPUs aimed at scaling performance for next-generation workloads.
The F3070X combines FPGA programmability with CPU integration in a hardware-programmable NIC, a design intended to eliminate network bottlenecks and speed up AI pipelines, disaggregated storage, and cybersecurity tasks. Customers can customize hardware and software configurations for their workloads, with use cases spanning real-time data movement, compression, and AI coprocessing. Napatech will demonstrate the DPU at Altera Innovator Day in San Jose, showcasing acceleration for AI storage and backend infrastructure.
Executives from both companies positioned the release as a major step for datacenter operators beyond the largest hyperscalers. Jarrod Siket, Chief Product & Marketing Officer at Napatech, said: “By partnering with Altera, we’re bringing this proven design to the next wave of cloud, enterprise, telecom, and AI datacenter operators — unlocking the same transformative benefits at every scale.”
• Napatech F3070X DPU delivers 400G acceleration using Altera Agilex FPGA and Intel Xeon D
• Targets AI, cloud, telecom, and enterprise datacenter workloads
• Supports programmable hardware and customizable software stacks
• Live demonstrations at Altera Innovator Day include AI storage acceleration and FPGA coprocessing
🌐 Analysis: The DPU launch marks Napatech’s move to extend FPGA-based acceleration from hyperscalers into broader markets, leveraging Altera’s common acceleration platform. The strategy mirrors efforts by NVIDIA with BlueField DPUs and AMD with Pensando, as vendors push DPUs and SmartNICs deeper into enterprise and AI infrastructure.
Napatech A/S (OSE: NAPA.OL) is a Denmark-based company headquartered in Copenhagen that develops programmable network acceleration solutions designed to improve performance in data centers, cloud, telecom, and AI infrastructure environments. The company specializes in SmartNICs and Data Processing Units (DPUs) that leverage FPGA-based acceleration to offload and secure workloads such as networking, storage, cybersecurity, and AI pipelines. Founded in 2003, Napatech is led by CEO Henrik Brill Jensen, who has a background in telecommunications and network systems, and is supported by a management team with expertise spanning hardware, software, and FPGA design. Napatech’s technology centers on its production-grade acceleration platform, which integrates FPGA programmability with software frameworks for high-throughput, ultra-low-latency packet capture, classification, and analysis. Its core product portfolio includes programmable SmartNICs and, more recently, the F3070X DPU launched in 2025, built on Intel Altera Agilex FPGA and Xeon D processors. The company is publicly traded on the Oslo Stock Exchange.
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