The OIF has published “Common Electrical (I/O) CEI 4.0” with a focus on Serdes standards for 56 Gbps.
The result is a number of carefully optimized channel definitions, paving the way for a range of interoperable solutions at 56 Gbps data rates. Key to this effort was aiming for the lowest possible power dissipation for each application while balancing link budget and latency. At this time the OIF is releasing CEI 4.0 with the following new clauses:
- CEI-56G-USR-NRZ: Ultra Short Reach, die-to-die inside muti-chip-modules, NRZ modulation
- CEI-56G-XSR-NRZ: Extra Short Reach, chip-to-driver, NRZ modulation
- CEI-56G-VSR-PAM4: Very Short Reach, chip-to-module, PAM-4 modulation
- CEI-56G-MR-PAM4: Medium Reach, chip-to-chip, one connector, PAM-4 modulation
- CEI-56G-LR-PAM4: Long Reach, chip-to-chip, two connectors over backplane, PAM-4 modulation
- CEI-56G-LR-ENRZ: Long Reach, chip-to-chip, two connectors over backplane, ENRZ modulation
“The industry continues to face challenges for diverging requirements regarding link latency and concerns with power consumption at the higher data rates,” said Klaus-Holger Otto of Nokia and the OIF Technical Committee Chair. “Documenting channel definitions in more granular reaches and multiple modulation schemes allows for the optimization of silicon chip designs, channel architectures and network operator use cases. These parameters for 56 Gbps will be used as building blocks for protocol specifications written by other organizations across the industry so the forum wanted to provide definitions that met their unique needs.”
