OIF has taken a major step toward redefining the electrical backbone of next-generation compute systems with the release of its Next Generation CEI-448G Framework Document. The new framework, introduced at OIF’s Q4 2025 meeting in Busan, South Korea, outlines the roadmap for electrical interfaces capable of 448 Gbps per lane—nearly doubling today’s 224 G lanes and setting the pace for 1.6 Tbps and 3.2 Tbps architectures that will power AI factories, hyperscale data centers, and exascale HPC systems.
Moving to 448 G per lane represents one of the largest electrical signaling leaps in decades. At these speeds, designers face severe challenges in maintaining signal integrity, power efficiency, and latency across chiplet, package, and board-level interconnects. The OIF framework identifies key technical focus areas—including advanced modulation such as PAM6 and PAM8, enhanced FEC architectures, and new measurement methodologies—to ensure interoperability across short-reach (XSR), very-short-reach (VSR), mid-reach (MR), and long-reach (LR) applications. This effort builds on more than 25 years of OIF leadership in defining electrical interface generations from CEI-56G to CEI-224G.
More than 150 engineers and industry leaders attended the Busan meeting to advance work across optical, electrical, and management interfaces. The event also featured a keynote by Professor Hoi-Jun Yoo of KAIST, who discussed South Korea’s AI-PIM semiconductor initiatives and their alignment with next-generation interconnect standards. OIF’s next meeting will take place February 9–13, 2026, in Palm Springs, California.
• CEI-448G enables a new class of high-density, low-latency, and power-optimized electrical links for AI and HPC systems.
• The framework explores modulation, FEC, and signal-integrity approaches to sustain 448 Gbps per lane across multiple reaches.
• Derived from April’s 448G Signaling Workshop, the document guides future Implementation Agreements for 448G interoperability.
• The initiative supports the ecosystem transition toward 1.6 Tbps and 3.2 Tbps pluggable and co-packaged optics.
“This meeting in Busan reflects the best of what OIF stands for — global collaboration and technical leadership,” said Nathan Tracy, OIF President (TE Connectivity). “The CEI-448G Framework represents the collective expertise of our members, built through months of dialogue and industry input that began with the 448G Signaling Workshop in April.”
🌐 Analysis: Reaching 448 Gbps per lane marks a critical milestone for electrical I/O, as AI accelerators, network fabrics, and optical engines demand faster and denser interfaces. It positions OIF’s electrical roadmap in lockstep with emerging 1.6 T and 3.2 T optical modules, enabling seamless scaling between chip-to-chip and rack-to-rack domains. Competitors such as IEEE, PCI-SIG, and UEC are converging on similar signaling targets, underscoring an industrywide push to align PHY-layer standards for next-generation AI data centers.
 | OIF 448G Signaling Workshop Video SeriesWatch 20 exclusive expert videos recorded live at OIF’s 448G Signaling Workshop (April 2025), where technical leaders across the semiconductor, optical, and system communities explored the future of high-speed electrical interfaces. The series features insights from Broadcom, Marvell, Intel, Synopsys, Cadence, Keysight, Tektronix, Credo, Astera Labs, Alphawave Semi, TE Connectivity, Cisco, Ciena, Ayar Labs, Lumentum, NVIDIA, AMD, Molex, Anritsu, and OIF leadership — covering key topics including PAM6/PAM8 modulation, FEC evolution, packaging, and advanced signal-integrity testing. Explore how the ecosystem is collaborating on the next generation of interoperable electrical interfaces driving AI, HPC, and cloud infrastructure. ▶ Watch the OIF 448G Workshop Videos |
