The OIF has launched a CEI-112G-XSR project for Die-to-Die (D2D) and Die-to-Optical Engine (D2OE) Common Electrical Interface, which will enable intra-package interconnects to optical engines or between dies with high throughput density and low normalized power operating in the data rate range of 72-116 Gbps with a reach up to 50 mm.
In addition to the already existing CEI-112G-MCM OIF project, which is dedicated to wide, high bandwidth CMOS-to-CMOS interconnects, the new CEI-112G-XSR project proposes to support technology mix, in particular CMOS-to-SiGe (Silicon Germanium), which is frequently used to build optical engines. System-in-package (SIP) leads to a requirement of supporting up to 50 mm trace length between the multiple chips on a common (organic) package substrate.
The working group for the CEI-112G-XSR project has identified the following benefits for OIF members:
- allow lower normalized power, double shoreline throughput density and provide a multi-source 72-116 Gbps D2D and D2OE electrical I/O interface. This will enhance the integration, normalized power reduction, and cost reduction for integrated OE, multiple-die SIPs.
- enable 1 to N lanes of 72-116 Gbps electrical I/Os (e.g. on ASIC/FPGA/OE).
“We jointly designed this project to address the problem of integrating multiple dies, including driver devices for optical engines on non-CMOS technologies, onto a common substrate within a large multi-chip-package design. Supporting this mix of technology allows combining the high logic density of CMOS devices with the high drive strength of analog components,” explained Klaus-Holger Otto of Nokia and OIF Technical Committee Chair.
