PCI-SIG has officially ratified the PCI Express (PCIe) 7.0 specification, delivering 128.0 gigatransfers per second (GT/s) per lane and up to 512 GB/s of bi-directional bandwidth in a 16-lane configuration. Released to members on June 11, the PCIe 7.0 standard doubles the data rate of PCIe 6.0 and is designed to meet the bandwidth demands of compute-intensive sectors such as AI/ML, 800G Ethernet, cloud hyperscale infrastructure, and quantum computing.
Key features of PCIe 7.0 include PAM4 signaling, Flit-based (flow control unit) encoding, and enhanced power efficiency, while maintaining full backward compatibility with earlier PCIe generations. The new standard aligns with PCI-SIG’s established cadence of doubling IO bandwidth approximately every three years. Work is already underway on pathfinding for the PCIe 8.0 specification, signaling continued momentum in high-speed interconnects across the ecosystem.
Alongside the PCIe 7.0 release, PCI-SIG introduced a major enhancement to support optical interconnects. A new Optical Aware Retimer Engineering Change Notice (ECN) updates the PCIe 6.4 and 7.0 specs to enable standardized PCIe operation over optical fiber using retimer-based solutions. This marks a pivotal step toward mainstream adoption of optical links in data center and AI accelerator topologies.
• PCIe 7.0 delivers up to 512 GB/s bi-directionally over x16 using 128.0 GT/s signaling
• Implements PAM4 signaling and Flit-based encoding for improved performance
• Supports AI, HPC, 800G Ethernet, and quantum computing workloads
• Optical Aware Retimer ECN enables PCIe operation over fiber links
• Backward compatible with prior PCIe generations
“As artificial intelligence applications continue to scale rapidly, the next generation of PCIe technology meets the bandwidth demands of data-intensive markets deploying AI, including hyperscale data centers, high performance computing (HPC), automotive and military/aerospace,” said Al Yanes, PCI-SIG President and Chairperson.
- Compared to PCIe 6.0, the PCIe 7.0 specification doubles the raw bit rate from 64.0 GT/s to 128.0 GT/s and doubles the total bi-directional bandwidth from 256 GB/s to 512 GB/s for a x16 configuration. While both generations use PAM4 signaling and Flit-based encoding—introduced in PCIe 6.0—PCIe 7.0 delivers enhanced power efficiency and signal integrity improvements optimized for longer reach and higher density deployments. Additionally, PCIe 7.0 integrates early support for optical connectivity via the new Optical Aware Retimer ECN, marking a significant architectural advancement not present in PCIe 6.0, which was still focused on traditional copper-based interconnects. These enhancements position PCIe 7.0 as a more scalable foundation for data center and AI workloads pushing toward higher aggregate throughput.
