PCI-SIG set the timeline for its next leap in interconnect performance, announcing that the PCI Express (PCIe) 8.0 specification will reach 256.0 GT/s and is targeted for release to members by 2028. The move continues the group’s cadence of doubling PCIe bandwidth roughly every three years, ensuring compatibility across client, server, HPC, and hyperscale data center environments.
The PCIe 8.0 standard aims to deliver up to 1 TB/s of bi-directional throughput on a x16 configuration, targeting workloads in AI/ML, quantum computing, edge systems, automotive, aerospace, and defense. The roadmap also calls for reviews of new connector technologies, latency and FEC confirmation, protocol enhancements, and techniques to improve power efficiency, while maintaining backward compatibility with prior generations.
Analysts note that hyperscale operators are only beginning deployments of PCIe 6.0 and showing interest in PCIe 7.0, underscoring the industry’s rapid acceleration in bandwidth needs. By extending the roadmap through PCIe 8.0, PCI-SIG reinforces its role in sustaining interconnect scalability across multiple generations of data-intensive applications.
• PCIe 8.0 will double PCIe 7.0 bandwidth to 256.0 GT/s
• Target throughput: 1 TB/s bi-directionally over x16 links
• Release to PCI-SIG members expected by 2028
• Roadmap covers AI/ML, quantum, edge, automotive, HPC, aerospace, and hyperscale data centers
• Objectives include connector review, protocol enhancements, latency and reliability targets, and improved power efficiency
• Full backward compatibility with earlier PCIe generations
“Following this year’s release of the PCIe 7.0 specification, PCI-SIG is excited to announce that the PCIe 8.0 specification will double the data rate to 256 GT/s, maintaining our tradition of doubling bandwidth every three years to support next-generation applications,” said Al Yanes, PCI-SIG President and Chairperson.
🌐 Why it Matters: The Peripheral Component Interconnect (PCI) standard was first introduced by Intel in 1992 as a way to unify system I/O and enable plug-and-play expansion cards for PCs and servers. In 1992, PCI-SIG (PCI Special Interest Group) was formed as an open standards consortium to manage and evolve the specification. Over three decades, PCI-SIG has guided the transition from the parallel PCI bus to PCI Express, introduced in 2003, which became the foundational interconnect for graphics, networking, storage, and accelerators. Each generation has doubled bandwidth, maintaining backward compatibility while scaling from desktop PCs to hyperscale data centers. The announcement of PCIe 8.0 underscores PCI-SIG’s ability to sustain this cadence through 2028, ensuring the technology remains relevant for AI, HPC, and emerging computing models.
| Standard | Year Introduced | Data Rate / Bandwidth | Notes |
|---|---|---|---|
| PCI | 1992 | 133 MB/s (32-bit, 33 MHz) | Intel’s original parallel bus standard |
| PCI-X | 1998 | Up to 1 GB/s | Extended PCI for servers and workstations |
| PCIe 1.0 | 2003 | 2.5 GT/s (~250 MB/s per lane) | First serial-based PCIe standard |
| PCIe 2.0 | 2007 | 5.0 GT/s (~500 MB/s per lane) | Doubled per-lane throughput |
| PCIe 3.0 | 2010 | 8.0 GT/s (~1 GB/s per lane) | Widely adopted in servers & GPUs |
| PCIe 4.0 | 2017 | 16 GT/s (~2 GB/s per lane) | First to break 1 TB/s on x16 config |
| PCIe 5.0 | 2019 | 32 GT/s (~4 GB/s per lane) | Targeted HPC & early AI workloads |
| PCIe 6.0 | 2022 | 64 GT/s (~8 GB/s per lane) | Introduced PAM4 signaling & FEC |
| PCIe 7.0 | 2025 | 128 GT/s (~16 GB/s per lane) | First data center deployments underway |
| PCIe 8.0 | 2028 (planned) | 256 GT/s (~32 GB/s per lane) | Up to 1 TB/s on x16, aimed at AI & quantum |
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