POET Technologies and Sivers Semiconductors have formed a strategic collaboration to co-develop External Light Source (ELS) modules designed for Co-Packaged Optics (CPO) and AI infrastructure. The agreement merges POET’s Optical Interposer platform with Sivers’ distributed feedback (DFB) laser technology to deliver scalable, high-performance, and cost-optimized light sources for hyperscale data centers and AI clusters.
The companies plan to address key challenges in CPO adoption, including power efficiency, form factor, and manufacturability. By using wafer-level production and chip-scale photonic integration, the jointly developed modules aim to lower costs and simplify large-scale deployments. POET and Sivers target early prototypes for customer evaluation in the first half of 2026 and expect production readiness by the end of 2026.
Analysts estimate the emerging ELS market for CPO solutions could exceed $1 billion annually, with AI optical connectivity already representing more than $50 billion in market value. “Together, we aim to deliver a new class of external light source modules that address key technical challenges in co-packaged optics and enable our customers to scale efficiently into the AI-driven future,” said Vickram Vathulya, CEO of Sivers Semiconductors.
• POET and Sivers will co-develop ELS modules for CPO and AI data centers
• Solution integrates POET’s Optical Interposer with Sivers’ high-power DFB lasers
• Wafer-level manufacturing and chip-scale photonic integration to reduce cost and improve scalability
• Customer prototypes targeted for 1H 2026, production readiness by end of 2026
• Market opportunity estimated at $1B+ annually for ELS supporting CPO deployments
🌐 Analysis: This collaboration positions POET and Sivers to capitalize on the accelerating shift to co-packaged optics in AI infrastructure. Competing players such as Ayar Labs, Lightmatter, and Broadcom are also advancing CPO ecosystems, but POET’s interposer approach combined with Sivers’ high-power lasers provides a differentiated, integrated pathway to address scaling challenges. The 2026 timeline aligns with hyperscaler adoption cycles as AI workloads continue to drive demand for higher-bandwidth, lower-latency interconnects.
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