PowerLattice emerged from stealth with a $25 million Series A round to commercialize a power-delivery chiplet designed to cut compute power needs by more than 50% for next-generation AI accelerators. The startup says its on-package architecture shortens the power path and removes resistive losses that increasingly constrain GPUs now pushing beyond 2 kW per device. Playground Global and Celesta Capital co-led the round, with participation from additional investors.
The company’s design introduces miniaturized on-die magnetic inductors, vertical packaging, and a programmable control layer to deliver power directly inside the processor package. PowerLattice claims the approach reduces throttling, improves compute utilization, and enables more AI compute per rack. The chiplet integrates into existing SoC designs and is already sampling for 1 kW-class GPUs, CPUs, and accelerators.
Founded by Peng Zou, Gang Ren, and Sujith Dermal—veterans of Qualcomm, NUVIA, and Intel—the company is positioning its technology as a response to the data center “power wall,” with U.S. AI energy usage projected to triple by 2028. PowerLattice has raised $31 million to date and operates from Camas, Washington, with an additional office in Chandler, Arizona.
• Series A: $25M led by Playground Global and Celesta Capital
• Product: On-package power-delivery chiplet for AI accelerators
• Efficiency impact: Cuts compute power requirements by >50%
• System impact: Reduces power-related throttling and increases compute utilization
• Readiness: Silicon in hand; engineering samples underway for 1 kW+ GPUs and CPUs
• Team: Founders with experience in integrated magnetics, analog ICs, and power management
• Footprint: Headquartered in Camas, WA; office in Chandler, AZ
“Power is the defining challenge for AI’s future,” said Peng Zou, Co-Founder and CEO of PowerLattice.
🌐 Analysis: Power delivery has become a first-order limit for high-density AI clusters, with GPU power envelopes climbing from 700 W to well above 1.5 kW in less than three years. PowerLattice enters a competitive but rapidly expanding segment that includes on-package VRM strategies from hyperscalers, advanced PDN designs in next-gen NVIDIA and AMD platforms, and emerging chiplet ecosystems from Intel and TSMC. The success of PowerLattice’s chiplet will hinge on integration ease, thermal behavior, manufacturability, and gains validated in large-scale AI clusters.
