Rapidus announced a strategic collaboration with Keysight to co-develop a high-precision process design kit (PDK) and improve yield for its 2nm gate-all-around (GAA) logic node. The agreement taps Keysight’s parametric test and new Wafer Operations Analytics Suite for root-cause analysis, feeding Rapidus’ Design-Manufacturing Co-Optimization (DMCO) flow and its “Manufacturing-for-Design” data loop. Rapidus targets an initial PDK release for early customers in Q1 2026.
The work runs alongside Rapidus’ pilot activity at IIM-1 in Chitose, Hokkaido, where the company started prototyping 2nm GAA devices and completed first EUV exposures earlier this year. Rapidus’ next-gen foundry model—Rapid and Unified Manufacturing Service (RUMS)—centers on 100% single-wafer processing to accelerate turn-around time and enable tighter design-to-fab feedback.
Keysight’s analytics will be used to isolate defect mechanisms and parametric drift, with results flowing into PDK correlation for devices, circuits and process modules. The companies said the goal is faster, more accurate PDK models that raise first-silicon success and shorten learning cycles on Rapidus’ 2nm line.
- Scope: Build a high-precision PDK for Rapidus’ 2nm GAA, informed by fab-side data and Keysight’s parametric testing and analytics.
- Tools: Keysight Wafer Operations Analytics Suite for rapid root-cause isolation across wafer, device and circuit levels.
- Timeline: Initial 2nm PDK to selected customers by Q1 2026; IIM-1 pilot line already producing 2nm GAA test structures with measured electrical characteristics.
- Foundry model: RUMS single-wafer processing + DMCO/MFD/“Raads” AI-assisted design to compress design/manufacturing cycles.
- Adjacent ecosystem: Recent Siemens collaboration to co-develop Calibre-based PDK and reference flow; Cadence collaboration on AI-driven design/IP for 2nm and BSPDN.
“Rapidus is dedicated to advancing the co-optimization of manufacturing and design…,” said Dr. Atsuyoshi Koike, CEO of Rapidus.
🌐 Analysis
Rapidus positions itself as Japan’s advanced-logic foundry for sovereign and commercial demand, with a mission to deliver fast, small-lot, bespoke chips and chiplets on a leading 2nm GAA process. Its business model hinges on RUMS (single-wafer flow) to capture richer in-line data and tighten DMCO loops, complemented by “Raads” AI-assisted design. The company began 2nm prototyping at IIM-1 and installed Japan’s first ASML NXE:3800E EUV system to support its 2027 mass-production target.
Funding and government backing remain substantial. Japan has agreed to provide up to ¥920 billion (~$6B) in subsidies tied to Rapidus’ R&D push, with additional FY2025 allocations reported (~¥200 billion) as the government shapes long-term legislation to support advanced chip production. NEDO approved Rapidus’ FY2025 plan and budget for 2nm integration, short-TAT manufacturing, and chiplet/package R&D. Locally, Hokkaido’s government, NY CREATES, and others have set workforce collaboration to build talent pipelines around Albany NanoTech and IIM-1.
Rapidus’ partner network spans IBM (Albany NanoTech) for nanosheet GAAFET R&D, imec for advanced process collaboration, Siemens EDA for Calibre-based PDK and reference flow, Cadence for AI-driven 2nm flows and IP, and now Keysight for fab analytics and PDK accuracy. Earlier ecosystem notes include PFN/Sakura Internet on Japan-made AI infrastructure. Taken together, the stack—EUV at IIM-1, DMCO/RUMS operations, and a deep design/test ecosystem—aims to compress time-to-tape-out and diversify foundry supply beyond Taiwan and Korea. Execution risk remains high, but the cadence of milestones in 2024–2025 shows steady progress toward the 2027 goal.
🌐 We’re tracking the latest developments in networking silicon. Follow our ongoing coverage at: https://convergedigest.com/category/semiconductors/
