SiFive, which traces its heritage back to the team that developed the RISC-V instruction set architecture (ISA) at the University of California, Berkeley, launched its latest designs aimed at high-performance AI workloads in highly-scalable compute clusters.
At a press event on September 17 in Santa Clara, SiFive executives highlighted the pivotal role the RISC-V architecture is playing, advancing from embedded applications to automotive, edge and now AI compute clusters. They provided updates on SiFive’s strategic roadmap and business momentum, emphasizing RISC-V’s efficiency for AI workloads. The XM Series, with its scalar, vector, and matrix engines, delivers exceptional memory bandwidth efficiency and maintains SiFive’s reputation for high performance per watt in compute-intensive applications.
SiFive’s XM Series features four X-Cores per cluster, delivering 16 TOPS (INT8) or 8 TFLOPS (BF16) per GHz, with each cluster sustaining 1TBps of memory bandwidth. The clusters can access memory through either a high-bandwidth port or a CHI (Coherent Hub Interface) port, which enables efficient coherent memory access across clusters. This allows multiple processing units to share and access data without the need for additional synchronization. By integrating both high-bandwidth and CHI ports, the XM Series offers flexible memory access, making it ideal for complex, multi-cluster AI systems and ensuring seamless compatibility with a wide range of architectures. SiFive envisions these systems being deployed either without a host CPU or alongside RISC-V, x86, or Arm-based architectures, providing broad flexibility for AI integration across industries.
The company also revealed plans to open source a reference implementation of its SiFive Kernel Library (SKL) as part of its ongoing support for the RISC-V ecosystem.
• SiFive launches Intelligence XM Series for AI workload acceleration.
• XM Series integrates scalar, vector, and matrix engines.
• 16 TOPS (INT8) and 8 TFLOPS (BF16) per GHz per cluster.
• 1TBps sustained memory bandwidth per cluster.
• SiFive announces open sourcing of SiFive Kernel Library (SKL).
• XM Series targets markets including IoT, data centers, and automotive.
“AI plays to SiFive’s strengths with performance per watt and our unique ability to help customers customize their solutions,” said Patrick Little, CEO of SiFive.
“RISC-V was originally developed to efficiently support specialized computing engines including mixed-precision operations,” said Krste Asanovic, SiFive Founder and Chief Architect. “This, coupled with the inclusion of efficient vector instructions and the support of specialized AI extensions, are the reasons why many of the largest datacenter companies have already adopted RISC-V AI accelerators.”
