Soft Machines, a start-up based in Santa Clara, California with development offices in India and Russia, unveiled a new processing architecture based on the concept of “virtual cores” and “virtual hardware threads.”
Unlike conventional microprocessors based on CISC and RISC architectures that make use of “physical cores” and “software threads,” the Soft Machines’ VISC architecture enables dynamic allocation and sharing of resources across cores. The company claims its design achieves 3-4 times more instructions per cycle (IPC), resulting in 2-4 times higher performance per watt on single- and multi-threaded applications. The architecture also leverages a light-weight “virtual software layer”, something the company believes will can give it the flexibility to adapt to new software ecosystems.
“We founded Soft Machines with the mission of reviving microprocessor performance-per-watt scaling. We have done just that with the VISC architecture, marking the start of a new era of CPU designs,” said Soft Machines co-founder, president and CTO Mohammad Abdallah. “CPU scaling was declared dead when the power wall forced CISC- and RISC-based designs into multi-core implementations that require unrealistically complex multi-threading of sequential applications. The VISC architecture solves this problem ‘under the hood’ by running virtual hardware threads on virtual cores that far exceed the efficiency of software multi-threading.”
The company has raised over $125 million in venture funding to date. So far, it has filed for over 75 U.S. patents. Soft Machines now has working silicon, proving out its design.
- Soft Machines was founded seven years ago by Mohammad Abdallah and Mahesh Lingareddy. Prior to founding Soft Machines, Mr. Abdallah worked from 1995 to 2005 as a computer architect at Intel, where he held a series of positions, most recently as a Senior Architect in Intel’s Microprocessor Architecture Group. Mr. Lingareddy also previously worked at Intel, where he was a Design Manager in Intel’s Microprocessor Product Group.
