Synopsys expanded its collaboration with TSMC to enable 2D and 3D design solutions across advanced nodes including N3C, N3P, N2P, and A16. The companies certified key Ansys (part of Synopsys) simulation and analysis tools and introduced an AI-assisted photonics optimization workflow for TSMC’s compact universal photonic engine (COUPE) platform. The joint effort targets faster, more reliable chip development for AI acceleration, high-speed data communications, and advanced computing.
The multiphysics flow brings together Ansys RedHawk-SC, RedHawk-SC Electrothermal, and Synopsys 3DIC Compiler for hierarchical thermal-aware and voltage-aware timing, aimed at large 3DIC and multi-die designs. An AI-driven photonics path leverages Ansys optiSLang, Ansys Zemax OpticStudio, and Ansys Lumerical FDTD—including inverse design of custom grating couplers—to shorten iteration cycles and improve optical coupling quality on COUPE.
Certification updates span power integrity, electromagnetic extraction, and ESD signoff. Ansys RedHawk-SC and Totem cover N3C, N3P, N2P, and A16; Ansys HFSS-IC Pro is certified for N5 and N3P; and Ansys PathFinder-SC adds an ESD current density/P2P checker for N2P with support for complex 3DIC topologies. Synopsys and TSMC also plan the first photonic design kit for the upcoming A14 process in the latter part of 2025.
- Ansys RedHawk-SC & Totem: power integrity signoff for TSMC N3C, N3P, N2P, A16
- Ansys HFSS-IC Pro: die-level EM extraction certified on TSMC N5 and N3P
- Ansys PathFinder-SC: new ESD CD/P2P checker certified for N2P; 3DIC/multi-die support
- Multiphysics 3DIC flow: RedHawk-SC Electrothermal + Synopsys 3DIC Compiler for hierarchical thermal/voltage-aware timing
- Photonics on COUPE: AI-assisted optimization with optiSLang, OpticStudio, and Lumerical FDTD (supports inverse-designed grating couplers)
- Roadmap: first photonic design kit for TSMC A14 targeted for late 2025
“TSMC’s advanced process, photonics, and packaging innovations are accelerating the development of high-speed communication interfaces and multi-die chips that are essential for high-performance, energy-efficient AI systems,” said Aveek Sarkar, director of the ecosystem and alliance management division at TSMC.
🌐 Analysis: The move reinforces Synopsys’ role as a primary enablement partner for TSMC across electronic and photonic design flows as AI and 3DIC drive demand for tighter multiphysics signoff. It follows similar expansions by EDA rivals—such as Cadence’s recent TSMC updates—highlighting a broader ecosystem push to standardize verification and photonics design at advanced nodes.
🌐 We’re tracking the latest developments in networking silicon. Follow our ongoing coverage at: https://convergedigest.com/category/semiconductors/
🌐 We’re launching the “Data Center Networking for AI” series on NextGenInfra.io and inviting companies building real solutions—silicon, optics, fabrics, switches, software, orchestration—to share their views on video and in our expert report. To get involved, send a note to jcarroll@convergedigest.com or info@nextgeninfra.io.
