Tabula released an updated version of its Stylus compiler, offering new 3 × 40G-to-100G low-latency Ethernet bridge reference design, as well as a high-performance search engine soft IP core developed in collaboration with Algo-Logic Systems. The designed are aimed at next-generation 100G networking equipment.
The Tabula Stylus compiler provides a synthesis, placement, and routing flow familiar to FPGA designers, using industry-standard RTL inputs and design constraints. The suite automatically exploits Tabula’s 3D Spacetime architecture.
