Cadence Expands TSMC Partnership with AI-Driven Design
Cadence announced a major expansion of its collaboration with TSMC to accelerate AI and HPC semiconductor design, covering advanced EDA ...
Tag: Cadence
Cadence and NVIDIA Break Power Analysis Limits for Billion-Gate AI Chips
Cadence has introduced the Palladium Dynamic Power Analysis (DPA) App, enabling semiconductor and systems designers to accurately measure and optimize ...
Cadence Delivers 12.8Gbps DDR5 Memory Subsystem
Cadence introduced the industry’s first DDR5 12.8Gbps MRDIMM Gen2 memory IP system solution on TSMC’s N3 process node, targeting AI, ...
Cadence and AST SpaceMobile Collaborate on Space-Based Cellular Broadband Network
Cadence Design Systems and AST SpaceMobile announced their collaboration to develop the AST5000 ASIC, a custom-designed chip powering AST SpaceMobile’s ...
Cadence previews Janus Network-on-Chip interconnect tool
Cadence Design Systems introduced its Janus Network-on-Chip (NoC) technology for managing data delivery between silicon components in complex SoCs and ...
Cadence completes acquisition of Rambus SerDes assets
Cadence Design Systems completed its previously-announced acquisition of the Rambus SerDes and memory interface PHY IP business. The deal brings ...
Cadence to Acquire Rambus SerDes PHY IP business
Cadence agreed to acquire the Rambus SerDes and memory interface PHY IP business. Financial terms were not disclosed. Rambus will ...
Cadence and GlobalFoundries collaborate on RF and mmWave
Cadence Design Systems has collaborated with GlobalFoundries (GF) to accelerate 5G and mobile design innovation through the delivery of the ...
Cadence collaborates with Samsung Foundry on process nodes down to 4nm
Cadence Design Systems has optimized its chip design software for Samsung Foundry’s advanced-process technologies down to 4nm. The companies said Cadence ...
Cadence says ready for TSMC’s 5nm FinFET
Cadence Design Systems confirmed that its digital, signoff and custom/analog tools have been certified for Design Rule Manual (DRM) and ...
MaxLinear employs Cadence for 400Gbps PAM4 chip using 16FF
MaxLinear used Cadence timing signoff tools to deliver its MxL935xx Telluride device, the first 400Gbps PAM4 system on chip (SoC) ...
Cadence intros deep neural-network accelerator AI processor IP
Cadence Design Systems introduced its deep neural-network accelerator (DNA) AI processor intellectual property for developers of articial intelligence semiconductors for ...
Cadence Collaborates with Intel on 14nm Tri-gate Design
Cadence Design Systems announced support for Intel’s 14nm Tri-Gate process technology to enable customers of Intel Custom Foundry. Cadence and ...
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