• Home
  • Events Calendar
  • Blueprint Guidelines
  • Privacy Policy
  • Subscribe to Daily Newsletter
  • NextGenInfra.io
No Result
View All Result
Converge Digest
Friday, April 10, 2026
  • Home
  • Events Calendar
  • Blueprint Guidelines
  • Privacy Policy
  • Subscribe to Daily Newsletter
  • NextGenInfra.io
No Result
View All Result
Converge Digest
No Result
View All Result

Home » Tech Update: Breaking through the Memory Wall

Tech Update: Breaking through the Memory Wall

September 22, 2023
in Video
A A

The memory wall has been a major challenge in scaling computing performance. This is about to change. Ahmad Danesh, Associate Vice President of Product Management from Astera Labs, highlights CXL at the Intel Innovation 2023 event in San Jose.

  • – Astera Labs has pioneered CXL and is the first to break through the memory wall.
  • – By utilizing its Leo CXL Memory Connectivity Platform in conjunction with 5th Gen Intel Xeon Scalable Processors, Astera Labs managed to boost memory bandwidth and capacity by 50%. This is particularly beneficial for AI applications and complex modeling such as computational fluid dynamics or data warehousing.
  • – What sets this solution apart is its ability to deliver these improvements while reducing latency by 25%. Plus, as a hardware-based solution, it can seamlessly integrate with any software application.

Check out other Tech Updates on our YouTube Channel (subscribe today): https://www.youtube.com/@NextGenInfra and check out our latest reports at: https://nextgeninfra.io/

Tags: AsteraCXL
ShareTweetShare
Previous Post

Spirent’s CloudSure stress tests 5G CNFs

Next Post

Sabey to build new data center campus in Oregon

Jim Carroll

Jim Carroll

Editor and Publisher, Converge! Network Digest, Optical Networks Daily - Covering the full stack of network convergence from Silicon Valley

Related Posts

Astera Labs Expands PCIe 6.x Interoperability Testing
Financials

Astera Labs Projects Continued Growth as Hyperscaler Adoption Accelerates

November 5, 2025
Marvell pushes ahead to 2nm with TSMC
Semiconductors

Marvell Expands CXL with CPU and DRAM Interoperability

September 2, 2025
Astera Labs Expands PCIe 6.x Interoperability Testing
Semiconductors

Astera Labs Q2 Revenue Jumps 150% YoY as PCIe 6

August 5, 2025
Astera Labs Expands PCIe 6.x Interoperability Testing
Data Centers

Astera Labs Backs NVIDIA’s NVLink Fusion

May 19, 2025
NVIDIA Video: Network Architecture for Scaling AI
Data Centers

Astera Labs video: Connectivity Fabrics for AI Clusters

February 11, 2025
Montage Technology Samples PCIe 6.x/CXL 3.x Retimer Chips
Data Centers

Montage Technology Samples PCIe 6.x/CXL 3.x Retimer Chips

January 22, 2025
Next Post
Sabey to build new data center campus in Oregon

Sabey to build new data center campus in Oregon

Categories

  • 5G / 6G / Wi-Fi
  • AI Infrastructure
  • All
  • Automotive Networking
  • Blueprints
  • Clouds and Carriers
  • Data Centers
  • Enterprise
  • Explainer
  • Feature
  • Financials
  • Last Mile / Middle Mile
  • Legal / Regulatory
  • Optical
  • Quantum
  • Research
  • Security
  • Semiconductors
  • Space
  • Start-ups
  • Subsea
  • Sustainability
  • Video
  • Webinars

Archives

Tags

5G All AT&T Australia AWS Blueprint columns BroadbandWireless Broadcom China Ciena Cisco Data Centers Dell'Oro Ericsson FCC Financial Financials Huawei Infinera Intel Japan Juniper Last Mile Last Mille LTE Mergers and Acquisitions Mobile NFV Nokia Optical Packet Systems PacketVoice People Regulatory Satellite SDN Service Providers Silicon Silicon Valley StandardsWatch Storage TTP UK Verizon Wi-Fi
Converge Digest

A private dossier for networking and telecoms

Follow Us

  • Home
  • Events Calendar
  • Blueprint Guidelines
  • Privacy Policy
  • Subscribe to Daily Newsletter
  • NextGenInfra.io

© 2025 Converge Digest - A private dossier for networking and telecoms.

No Result
View All Result
  • Home
  • Events Calendar
  • Blueprint Guidelines
  • Privacy Policy
  • Subscribe to Daily Newsletter
  • NextGenInfra.io

© 2025 Converge Digest - A private dossier for networking and telecoms.

This website uses cookies. By continuing to use this website you are giving consent to cookies being used. Visit our Privacy and Cookie Policy.
Go to mobile version