Tilera, a start-up based in San Jose, California, introduced its “TILE-Gx” 3000 processor family specifically designed to take on Intel’s Sandy Bridge as the workhorse for common cloud computing applications. 
Tilera’s TILE-Gx 3000 processors are optimized for cloud datacenters and promise a “10-fold performance-per-watt advantage over Intel’s SandyBridge processor family.”
The TILEGx-3000 series includes three processors to address different market segments: 36, 64 or 100 cores. The processors are implemented using the 40 nanometer TSMC fabrication process. Each core features a powerful three-issue, 64-bit ALU with an advanced virtual memory system. Each core includes 32 kilobytes (kB) of L1 I-cache, 32 kB of L1 D-cache and 256 kB L2 cache, with up to 32 megabytes L3 coherent cache across the device.
The first of the TILE-Gx family of processors, the 36-cores device, will be sampling in July of 2011, with the 64 and 100-core devices available early in 2012.
http://www.tilera.com
- In January 2011, Tilera raised $45 million in new funding for its TILE family of many-core processors for cloud computing and communications.
Tilera’s processors are based on its “iMesh” architecture that scales to hundreds of RISC-based cores on a single chip. Tilera has two product families: TILE64 processors and TILEPro processors, with its latest TILE-Gx family planned for early 2011.
The new funding was led by Artis Capital Management, that included investment from WestSummit Capital Management and Comerica Bank in addition to existing investors Walden International, Bessemer Venture Partners and Columbia Capital. Cisco Systems and Samsung Venture Investment Co. also participated, joining Tilera’s previous strategic investors: Broadcom, NTT Finance, VentureTech Alliance, and Quanta Computer.
- Tilera was founded in 2004 to bring to market the MIT research of Dr. Anant Agarwal who first created the mesh-based multicore architecture in 1996. The “Raw” project received multi-million dollar DARPA and National Science Foundation grants and spawned the development of the first tiled multicore processor prototype and associated multicore software in 2002.
