Toshiba announced 96-layer BiCS FLASH, its proprietary 3D flash memory, with 4-bit-per-cell (quad level cell, QLC) technology that boosts single-chip memory capacity to the highest level yet achieved. The advancement pushes the bit count for data per memory cell from three to four, thus significantly expanding capacity. The new product achieves the industry’s maximum capacity of 1.33 terabits for a single chip which was jointly developed with Western Digital Corporation.
A capacity of 2.66 terabytes can be achieved with a 16-chip stacked architecture in one package.
Toshiba Memory will begin sampling to SSD and SSD controller manufacturers from the beginning of September, and expects to start mass production in 2019.
Separately, Western Digital announced its second-generation, four-bits-per-cell architecture for 3D NAND using 96-layer BiCS4 technology. BiCS4 was developed at the joint venture flash manufacturing facility in Yokkaichi, Japan in partnership with Toshiba Memory Corporation. Consumer products marketed under the SanDisk brand are expected to begin shippint this year. Western Digital expects to deploy BiCS4 in a wide variety of applications from retail to enterprise SSDs.
