Toshiba Memory has developed a bridge chip for connecting flash memory chips into faster and higher capacity SSDs.
In SSDs, multiple flash memory chips are connected to a controller that manages their operation. As more flash memory chips are connected to a controller interface, operating speed degrades, so there are limits to the number of chips that can be connected. In order to increase capacity, it is necessary to increase the number of interfaces, but that results in an enormous number of high-speed signal lines connected to the controller, making it more difficult to implement the wiring on the SSD board.
Toshiba said it has overcome this problem with the development of a bridge chip that connects the controller and flash memory chips (Fig. 1), three novel techniques: a daisy chain connection including the controller and bridge chips in a ring shape; a serial communication using PAM 4; and a jitter improvement technique for eliminating a PLL circuit in the bridge chips. By using these techniques overhead of the bridge chips is reduced, and it is possible to operate a large number of flash memory chips at high speed with only a few high-speed signal lines.
The ring-shape configuration of the bridge chips and the controller reduces the number of transceivers required in the bridge chip from two pairs to one pair, it achieves chip area reduction of the bridge chip. In addition, adopting PAM 4 serial communication between the controller and the daisy-chained bridge chips lowers the operating speed in the bridge chips’ circuits and relaxes their required performance.
The prototype bridge chips were fabricated with 28nm CMOS process, and results were evaluated by connecting four bridge chips and a controller in ring-shape daisy chain.
