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Home » TSMC advances its 3DFabric chip stacking technologies

TSMC advances its 3DFabric chip stacking technologies

June 2, 2021
in Semiconductors
A A

TSMC cited progress with its “3DFabric” advanced packaging and chip stacking technologies at the company’s online 2021 Technology Symposium. 

TSMC will be offering larger reticle-size for both its InFO_oS and CoWoS® packaging solutions in 2021, enabling larger floor plans for chiplet and high-bandwidth memory integration. Additionally, the chip-on-wafer (CoW) version of TSMC-SoIC will be qualified on N7-on-N7 this year with production targeted for 2022 at a new fully-automated factory.

In addition, TSMC is introducing its N5A process node, the newest member of the 5nm family and aimed at satisfying the growing demand for computing power in newer and more intensive automotive applications such as AI-enabled driver assistance and the digitization of vehicle cockpits.

TSMC also said its N3 process node technology is poised to begin volume production in the second half of 2022.

https://pr.tsmc.com/english/news/2831

Tags: SiliconTSMC
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