The Universal Chiplet Interconnect Express (UCIe) Consortium has unveiled its 2.0 Specification, marking a significant advancement in the standardization of system architecture for chiplet manageability. The new specification addresses key design challenges in testability, manageability, and debugging (DFx) throughout the System-in-Package (SiP) lifecycle, from initial sorting to field management. With the introduction of optional manageability features and the UCIe DFx Architecture (UDA), a management fabric within each chiplet facilitates vendor-agnostic interoperability, offering a flexible and unified approach to SiP management and DFx operations.
The 2.0 Specification also enhances support for 3D packaging, providing higher bandwidth density and improved power efficiency compared to 2D and 2.5D architectures. UCIe-3D is optimized for hybrid bonding with functional bump pitches ranging from 10-25 microns down to as small as 1 micron, offering both flexibility and scalability. Additionally, the specification includes optimized package designs for interoperability and compliance testing, establishing an initial framework for physical, adapter, and protocol compliance. According to Cheolmin Park, UCIe Consortium President and Corporate VP at Samsung Electronics, the 2.0 Specification aims to meet the diverse needs of the rapidly evolving semiconductor industry, fostering a robust open chiplet ecosystem.
Highlights of the UCIe 2.0 Specification:
- Holistic support for manageability, debug, and testing for any SiP construction with multiple chiplets.
- Support for 3D packaging to significantly enhance bandwidth density and power efficiency.
- Improved system-level solutions with manageability defined as part of the chiplet stack.
- Optimized package designs for interoperability and compliance testing.
- Fully backward compatible with UCIe 1.1 and UCIe 1.0.
