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Home » Wafer-Scale CPO + Wafer-Scale AI Computing

Wafer-Scale CPO + Wafer-Scale AI Computing

April 30, 2025
in Video
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Ranovus is working with Cerebras Systems under a $45 million DARPA contract to develop a next-generation high-performance computing platform that integrates Ranovus’ wafer-scale co-packaged optics with Cerebras’ wafer-scale AI chips.

Hamid Arabzadeh, CEO from Ranovus explains:

– Wafer-scale co-package optics enables access to interfaces in the middle of multi-GPU wafers, advancing beyond single-die solutions
– The technology delivers two orders of magnitude more capacity compared to current 1.6 terabit/second optical engines
– This paves the way for massive compute scaling with unprecedented interconnect capabilities while reducing power consumption

Want to be involved our video series? Contact info@nextgeninfra.io
https://ngi.fyi/ofc25-ranovus-hamid

Check out OFC Conference and Exposition 2025 videos here: https://ngi.fyi/ofc25yt

Tags: Ranovus
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Jim Carroll

Jim Carroll

Editor and Publisher, Converge! Network Digest, Optical Networks Daily - Covering the full stack of network convergence from Silicon Valley

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