Xilinx Demonstrates 10 Gbps Serial I/O PLD

Xilinx announced the successful demonstration of serial technology at 10 Gbps on a single channel using a standard CMOS logic process. Xilinx said parallel I/O schemes reach physical limitations at speeds greater than 1 Gbps, no longer providing a reliable and cost-effective means for high-speed signaling. In addition to providing higher performance, Serial I/O-based designs should bring cost advantages over parallel implementations through fewer device pins, reduced board space requirements, fewer PCB layers, easier layout of the PCB, and smaller connectors. Other advantages include reduced EMI and improved noise immunity. Xilinx’s solution is based on Non-Return to Zero (NRZ) signaling, and could be used for chip-to-chip, chip-to-module, and serial backplane applications.
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