Xilinx has announced what it claims is a disruptive integration and architectural technique for 5G wireless with the addition of RF-class analogue technology into its 16 nm All Programmable MPSoC products.
Xilinx’s new All Programmable RFSoCs eliminate the need for discrete data converters, providing a claimed 50-75% reduction in terms of power and footprint for 5G massive MIMO and millimetre-wave (mmWave) wireless backhaul applications.
The company noted that large scale 2D antenna arrays will be a key element for increasing spectral efficiency and network densification for 5G networks. The integration of ADCs and DACs into Xilinx’s All Programmable SoC devices is designed to enable radio and wireless backhaul units to meet previously unattainable power and form factor demands, while also allowing higher channel density.
In addition, the new RFSoC devices can also help manufacturers streamline design and development cycles and meet 5G deployment timelines.
Xilinx’s new All Programmable RFSoC devices offer features including:
1. Direct RF sampling to simplify analogue design and enhance accuracy and enable a smaller form factor and lower power consumption.
2. 12-bit ADCs supporting up to 4 GS/s, high channel count, with digital down-conversion.
3. 14-bit DACs supporting up to 6.4 GS/s, high channel count and digital up conversion.
The new RFSoC integrated subsystem specifically targets a range of applications including high bandwidth remote radio and backhaul systems for 5G deployments and remote node architectures (R-PHY) for DOCSIS 3.1 cable broadband systems.
