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Home » AppliedMicro Samples 28.1 Gbps CMOS PHY for 100GBASE-LR4

AppliedMicro Samples 28.1 Gbps CMOS PHY for 100GBASE-LR4

February 14, 2012
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AppliedMicro has begun sampling the world’s fastest CMOS PHY at 28.1Gbps. The new S28010 Gearbox integrated circuit is designed for next generation CFP optical modules compliant with 100GBASE-LR4, 100GBASE-ER4 and OTU4.4 standards, supporting optical connection speeds from 10Gbps to 100Gbps for high-end switching and routing equipment.

Until now, industry adoption efforts have been slowed by high-cost, power-hungry SiGe or FPGA integrated circuits that are limited and unable to provide transport-quality performance and reliability.

AppliedMicro said its 28010 Gearbox delivers SiGe-like performance in a reliable, low-power CMOS process and enables system designs with the flexibility to transport Ethernet, Fibre Channel and Optical Transport Network traffic.

AppliedMicro will demonstrate the S28010 Gearbox at OFC/NFOEC 2012 from March 6-8 in Los Angeles.

“Data center and access network developers have been eager for 100GBASE-R4 Gearbox devices that lower power and cost while improving reliability and availability,�? said George Jones, Vice President of AppliedMicro’s Transport Business Unit. “The S28010 is designed to allow module vendors to supply CFP-based solutions that support Ethernet, Fibre-channel and Optical Transport Networks using a single chip, exceeding jitter requirements in the process. The 28Gbps interface contains enhanced equalization for line-card compatibility with CFP2 and potentially CFP4 modules when they become available. The S28010 also integrates ODB precoding and decoding to support metro applications.”

AppliedMicro’s Gearbox translates the 10-lane, 10Gbps CAUI electrical interface to 4-lanes operating from 25.7 up to 28.1 Gbps. It is compliant with IEEE802.3ba, the CFP MSA and OIF-28G-SR standards. The fully-integrated single-chip solution reduces module bill of materials and with power consumption below 4 watts, it is less than 50 percent of comparable 2-chip BiCMOS solutions. The result is reduced system heat and lower operational costs without compromising performance.
http://www.apm.com

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