Cisco showcased its new 100 Gbps, CMOS-based transceiver technology at this week’s OFC/NFOEC 2013 event in Anaheim, California. The new technology, which Cisco describes a breakthrough for the rollout of 100G services, is powered by Cisco’s nLight silicon.
By integrating advanced optics in complementary metal oxide semiconductor (CMOS) technology, Cisco is able to significantly increase face-plate density for 100G pluggable optics.
The Cisco “CPAK” transceiver, which will initially be available on the Cisco ONS 15454 MSTP 100 G coherent transponder, reduces space and power requirements by over 70 percent compared with alternative transceiver form factors, such as CFP. Future routing and switching line cards will also incorporate CPAK technology.
“Cisco’s CMOS design allows us to utilize the immense and highly evolved CMOS IC fabrication industry, which delivers low-cost, highly integrated and reliable components,” said Bill Gartner, vice president and general manager of Cisco’s High End Routing and Optical business unit. “We see this as a critical differentiator to reduce the power, cost and size of components, and it will help make 100 gigabit as widely deployed as 10 gigabit is today. No other industry solution offers as much opportunity to reduce 100 gigabit deployment costs as the Cisco CPAK.”
Cisco’s first line card to incorporate CPAK technology is the 100Gbps CPAK Coherent DWDM line card, compatible with the ONS 15454 MSTP platform. The card uses Cisco’s 100GE IEEE standards-based LR4, SR10 and ER4 CPAK pluggables on the client interface and Cisco’ ultra long-haul coherent technology on the network facing (trunk) interface.
In addition, Cisco announced that its 100G DWDM powered by nLight technology can cover distances of up to 4,800 km without the need for signal regeneration. The density of the technology enables 6 x 100G Transponders in a 6 RU chassis, or the equivalent of 8.4 Terabits of I/O in a single rack.
Cisco also noted that its nLight silicon photonics could be further developed in state-of-the-art 28nm CMOS silicon to enable 400Gbps and 1 Tbps rates.
http://newsroom.cisco.com/press-release-content?type=webcontent&articleId=1157237
