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Home » Intel launches FPGA-based accelerator for 5G core and vRAN

Intel launches FPGA-based accelerator for 5G core and vRAN

February 26, 2019
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Intel is introducing an FPGA-based acceleration card for 5G core and virtualized radio access network solutions.

The Intel FPGA Programmable Acceleration Card N3000 is designed to accelerate network traffic for up to 100 Gbps and supports up to 9GB DDR4 and 144MB QDR IV memory for high-performance applications. Programmability and flexibility of an FPGA allow customers to create tailored solutions by utilizing reference IPs for networking function acceleration workloads such as vRAN, vBNG, vEPC, IPSec and VPP.

Affirmed Networks is using Intel’s FPGA PAC in a new solution for 5G core network (CN)/evolved packet core – a 200 Gbps/server that provides smart load balancing and CPU cache optimizations.

Rakuten, the soon to be the operator of Japan’s newest mobile network, is including Intel x86 and FPGA-based PAC for acceleration from the core to the edge to provide the first end-to-end cloud-native mobile network. Intel FPGA PAC N3000 is the distributed unit accelerator next to Intel® Xeon Scalable processor where Layer 1 functions, such as forward error correction and front haul transmission, are offloaded onto an Intel FPGA.

“As the mobile and telecommunications industry gears up for an explosion in internet protocol traffic and 5G rollouts, we designed the Intel FPGA PAC N3000 to provide the programmability and flexibility with the performance, power efficiency, density and system integration capabilities the market needs to fully support the capabilities of 5G networks,” stated Reynette Au, Intel vice president of marketing, Programmable Solutions Group.

“5G is a transformative technology, and it requires advanced network virtualization infrastructure coupled with an agile software architecture. Working with an Intel FPGA PAC N3000, we have developed a cloud-native, containerized solution for the 5G core and EPC – the first true 100G/CPU socket solution. The FPGA acceleration allows us to process this traffic load with 50 percent less CPU utilization2, providing significant room for growth,” said Ron Parker, chief architect at Affirmed Networks. “Intel FPGAs optimize software performance, lowering power consumption and latency for diverse quality of service characteristics across multiple 5G network slices.”

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