The Optical Internetworking Forum (OIF) unveiled a new Serial Look-Aside Interface (SLA) Implementation Agreement (IA) that gives users the ability to interface Network Processor Element (NPE) to look-aside devices such as co-processors and memories at bandwidth speeds up to 40 Gbps and up.
The Serial Look-Aside Interface IA, which was recently published by the OIF’s Physical and Link Layer (PLL) Working Group, upgrades the widely adopted LA-1 look-aside Interface between NPEs and network search elements such as memory and co-processors. This interface is often used between a network processor and a Ternary Content Addressable Memory (TCAM). The SLA IA builds upon the System Packet Interface – Scalable (SPI-S) implementation agreement, making the high-speed interface available for immediate deployment.
The SPI-S is the next-generation interface developed by the OIF to take advantage of serialization of physical interconnects. SPI-S is a robust, channelized, streaming-packet interface that scales from 6 Gb/s to hundreds of Gb/s for chip-to-chip and backplane applications. A successor to the widely deployed OIF SPI 4.2 interface, SPI-S leverages the OIF’s CEI-P to take advantage of high rate serial physical interconnects.
The SLA IA supports the transfer of command, date, result and maintenance traffic between host controller (ASIC, FPGA or NPE) and a look-aside co-processor. The Look-Aside Interface supports the transfer of status and maintenance information such as Credit Pool Status information or Signaling Data Transfers, in-band with commands.
“We expect the industry to benefit from the Serial Look-Aside Interface IA,” said David Stauffer, of IBM and the chair of the OIF’s PLL Working Group. “Currently interfaces between Network Processor Element devices and Content Addressable Memory (CAM) or other look aside elements use the Look Aside-1 (LA-1) interface, which is a parallel interface limited to 10Gb/s bandwidth. Now the industry has a standardized interface to transfer data between the NPE and CAM elements that scale to 40Gb/s and beyond to higher rates than the industry currently needs.”
The OIF also released a new version of the Common Electrical Interface Protocol (CEI-P) Implementation Agreement, which includes new clauses for mapping TFI-5 and TDM-P applications over a CEI-P layer. CEI-P clauses for TFI-5/TDM-P now enable a higher level of integration that supports greater data throughput within the same physical space, resulting in more cost effective and efficient operation. The TDM Fabric-to-Framer Interface (TFI) series of interfaces and their aggregation layer, TDM-Protocol (TDM-P), are important methods of transporting SONET/SDH and OTN TDM signals between devices. The CEI-P layer, a protocol layer for the Common Electrical Interface (CEI), was defined by the OIF in early 2006 as a low-level protocol building block that uses 64B/66B block coding and supports optional Forward Error Correction (FEC). This new revision of the CEI-P IA describes a mapping of the existing TFI and TDM-P protocols over CEI-P.
In addition, OIF members have re-elected Dave Stauffer of IBM as the chair of the Physical and Link Layer Working Group. Rod Smith of Tyco Electronics has been elected co-chair of the Marketing Awareness & Education committee.http://www.oiforum.com
