Sierra Monolithics introduced the world’s first 100G multiplexer with clock multiplier unit (CMU) and demultiplexer with clock and data recovery (CDR). The first in a planned family of 100G solutions, the devices are key components for equipment used in both the short-reach data center and high-performance computing market, as well as long-haul and metro carrier networks.
Sierra Monolithics’s Theta-100G solution includes the SMI10021 10:4 MUX/CMU and SMI10031 4:10 CDR/DEMUX devices. Each uses the same fourth-generation, 130-nanometer IBM 8HP bipolar complementary metal-oxide semiconductor (BiCMOS) silicon germanium (SiGe) process technology as the company’s recently introduced 40G solutions. These devices are available in a surface mount BGA (Ball Grid Array) package.
The company said BiCMOS is a natural choice for 100G because it is well suited for fast transistor switching requirements where low noise is essential. Bipolar SiGE results in higher gain, higher frequency, and lower noise floor as compared to CMOS, allowing transmission systems to meet stringent eye quality parameters. The Theta-100G chipset operates at 4 x 25.0 Gbps to 28.3 Gbps (100-113 Gbps) and incorporates an integrated, dual-polarization quadrature phase-shift keying (DP-DQPSK) modulation precoder function that makes 100G networks extremely resistant to the type of impairments that are often encountered in older fiber.
“Sierra Monolithics has built on the leadership foundation of our pioneering 40G family to deliver the industry’s first 100G MUX/CMU and CDR/DEMUX,” said Javed Patel, President and CEO of Sierra Monolithics. “This chipset will enable the development of 100G transponder modules and line cards that will relieve carriers’ increasingly congested network routes and significantly lower their transport costs per bit, while also increasing throughput in data center networks so they can support today’s exponentially growing demand for video, peer-to-peer and virtualization services.”
The Theta-100G chipset incorporates a 10×10.3Gb/s (MLD/CAUI) or 11×11.2Gb/s SFI-S interface on the client side, as well as a de-skew function in compliance with OIF SFI.S, plus a line side pre-skew function for the MLD/CAUI interface with a depth of 84UI. The inclusion of on-chip, selectable single- and dual-DQPSK precoding circuitry delivers high spectral efficiency, high optical signal-to-noise ratio sensitivity, and robustness against dispersion. The DQPSK precoding function is implemented with dual I/Q-interleaved outputs (4x28Gbps) for dual-polarized (DP-DQPSK) applications. The precoding function may also be configured to enable a single-pole 2x56Gb/s DQPSK modulation structure with a pair of external 2:1 multiplexers through use of the synchronous high-speed clocks which may be programmed to any desired clock-to-data skew.
Other features include on-chip industry-standard selectable phase detector on-chip dual-mode (PRWS) pattern generators and error checkers, and SPI control interfaces with clock rates to at least 150 MHz. Typical jitter swing is 3.7psec p-p typical, and the differential output level is 0.6 to 1.2V p-p. Power consumption is a low 4 Watts max with high-speed clock outputs disabled. The chipset will enable the development of 100G-capable line cards and transponders, and will support the 300-pin multisource agreement (MSA) pluggable module definition and, in the future, smaller form factors, as well.
http://www.monolithics.com
