Tabula, a start-up based in Santa Clara, California, introduced its suite of high-performance packet processing solutions aimed at 100G applications.
The technology focuses on routing of high-performance buses, on-chip RAM throughput, and timing closure for the ultra-high-performance functions required by 100G systems. Tabula will also leverage Intel’s 22nm Tri-Gate technology.
The packet processing solutions, combined with Tabula’s new ABAX2P1 3PLD, deliver processing of four 100G streams on a single chip, a search engine capable of supporting 100G packet traffic, and a 12x10G-to-100G bridge.
Tabula’s high-performance packet processing reference design suite is composed of:
- A 12x10G-to-100G bridge reference design kit, implementing an aggregation function commonly used in communications systems and using the ABAX2P1 device’s unique high performance commonly used in communications systems and using the ABAX2P1 device’s unique highperformancebus-handling capabilities.
- A 4x100G switch reference design kit, targeting data center migration from 10G to 40G and100G, is made possible by the ABAX2P1 device’s ability to process multiple 100G streams.
- A 2nd-generation Ternary Search Engine (TSE) reference design kit, delivering the highperformance search capabilities required for leading-edge routers and NGFW while showcasing the ABAX2P1 device’s unmatched RAM capabilities.
The company said its solution leverages innovations four key areas: Programmable 3D architecture, RTL compiler, leading-edge process technology using Intel’s 22nm Tri-Gate technology, and 3PLD devices.
“The capabilities we have demonstrated are simply out of reach of even the most advanced FPGAs,” said Dennis Segers, Tabula’s Chief Executive Officer. “With this comprehensive suite of programmable solutions, we are uniquely supporting the migration from 10G to 40G and 100G that is currently underway.”
