The Ultra Accelerator Link (UALink) Consortium, backed by AMD, Amazon Web Services (AWS), Astera Labs, Cisco, Google, HPE, Intel, Meta, and Microsoft, has officially incorporated and is now welcoming new members. The Consortium, originally founded as the UALink Promoter Group in May 2024, focuses on creating an open standard for high-speed, low-latency communication between AI accelerators and data center switches. UALink’s first open invitation offers Contributor membership to interested parties, allowing them to influence and shape the consortium’s specifications and access early development insights.
The UALink 1.0 specification will be released to Contributor members later this year, with a general review slated for the first quarter of 2025. This new specification supports up to 200 Gbps per lane for AI pod interconnections, scalable to 1024 accelerators, facilitating better memory access and smoother data transfers within data-intensive AI clusters. By creating a standard that accelerates interconnectivity, the consortium aims to optimize infrastructure for complex AI workloads, especially for next-generation data center AI applications.
Willie Nelson, President of the UALink Consortium, noted, “The UALink standard defines high-speed, low-latency communication for AI systems, and we encourage interested companies to join as Contributor members to help shape this open, high-performance accelerator interconnect.”
- Consortium leadership: AMD, Astera Labs, AWS, Cisco, Google, HPE, Intel, Meta, Microsoft
- Founded: May 2024, incorporated October 29, 2024
- UALink 1.0 Specification: Up to 200 Gbps per lane, scalable to 1024 accelerators
- Contributor membership: Available now, with the 1.0 spec review in Q1 2025
- Membership information: www.UALinkConsortium.org
“The release of UALink 1.0 in early 2025 marks a critical step toward an open industry standard, expanding AI accelerator interconnectivity,” added Kurtis Bowman, Chairperson, UALink Consortium.
