Xilinx unveiled a new architecture aimed at enabling the rapid deployment of multiple domain-specific FPGA platforms. At the heart of the “ASMBL” architecture is a modular framework of silicon subsystems, enabling a new FPGA development methodology. It makes use of advanced flip-chip packaging technology and eliminates geometric layout constraints associated with traditional chip design such as hard dependencies between I/O count and fabric array size. The ASMBL architecture also addresses the increasingly more stringent requirements for on-chip power and ground distribution by allowing power and ground to be placed anywhere on the chip.
Xilinx plans to base future Xilinx Platform FPGAs on the new architecture. Its next generation Virtex Series Platform, slated for first half of 2004, will embody the new architecture and deliver more than 1B transistors in a single device.
“Moore’s Law, as well as advances in packaging technologies, continue to propel programmable logic to new heights of capacity and performance” said Wim Roelandts, chairman and CEO at Xilinx. “The ASMBL architecture will allow Xilinx to further penetrate the $38 billion dollar logic markets with aggressive cost points never before possible.”
Since its 1998 introduction, Xilinx has shipped over 10 million Virtex FPGA devices.http:// www.xilinx.com
