Alphawave Semi has successfully taped out a 36G UCIe IP subsystem on TSMC’s 2nm (N2) process, becoming one of the first to demonstrate die-to-die connectivity on nanosheet technology. The IP is integrated with TSMC’s CoWoS® advanced packaging and achieves 11.8 Tbps/mm bandwidth density—providing a path to 64G UCIe and future chiplet-based AI platforms.
The new 36G subsystem supports UCIe 2.0 standards with ultra-low power, low latency, and advanced features such as per-lane health monitoring and extensive testability. It is compatible with multiple protocols, including PCIe, CXL, AXI, and CHI, via Alphawave Semi’s configurable Streaming Protocol D2D Controller.
This milestone builds on the recent Alphawave Semi AI Platform announcement, strengthening its ability to serve hyperscale AI and HPC markets with scalable open chiplet solutions. The collaboration with TSMC also signals readiness to accelerate UCIe-based ecosystem development across AI and cloud infrastructures.
“We’re proud to lead the industry into the N2 era with one of the first UCIe IP on this advanced node,” said Mohit Gupta, Senior VP & GM, Custom Silicon & IP, Alphawave Semi. “Our 36G subsystem validates a new class of high-density, power-efficient chiplet connectivity and paves the way for 64G UCIe and beyond—critical for AI and high-radix networking applications.”
- One of the first 36G UCIe IP subsystems taped out on TSMC 2nm process
- Integrated with CoWoS® advanced packaging delivering 11.8 Tbps/mm bandwidth density
- UCIe 2.0 compliant with multi-protocol support: PCIe, CXL, AXI, CHI
- Advanced capabilities: ultra-low power, low latency, per-lane health monitoring, and high testability
- Positioned for AI, HPC, and future chiplet-driven architectures
“Our latest collaboration with Alphawave Semi underscores our shared commitment to driving advancements in high-performance computing through design solutions that fully leverage the performance and energy-efficiency advantages of TSMC’s advanced process and packaging technologies,” said Lipen Yuan, Senior Director of Advanced Technology Business Development at TSMC.
- UCIe (Universal Chiplet Interconnect Express) is an open industry standard designed to enable high-bandwidth, low-latency die-to-die connectivity for chiplet-based architectures. The UCIe Consortium released version 2.0 of the specification in December 2023, expanding data rates up to 64G per lane and supporting a range of protocols such as PCIe, CXL, and custom streaming. The standard is rapidly gaining adoption across semiconductor, cloud, and AI ecosystem players, who are working to ensure interoperability across advanced packaging platforms like TSMC’s CoWoS and Intel’s EMIB.
